FIG. 1 is a block diagram of a prior art conventional Delay Locked Loop (DLL) 100. The main function of a DLL is to synchronize two clock signals by aligning their rising edges. An externally supplied clock signal CK is buffered by clock buffer 101 to provide a reference clock signal CKref that is coupled to a voltage controlled delay line (VCDL) 102 and a phase detector (PD) 104. The voltage controlled delay line 102 produces a DLL output clock signal CKout, which is a delayed version of CKref and is routed to various circuits within a device through a buffering structure referred to as a clock tree.
A feedback clock signal CKf is tapped at a terminal node of a branch of the clock tree or obtained by applying the output clock signal CKout to a replica of the clock tree branch, that is, a replica delay circuit 103 and fed back to the PD 104. The replica delay circuit 103 also known as a delay model or a clock tree branch replica, reproduces all delays added to the output clock signal CKout by the multi-stage buffering structure of the clock tree. The delays include all propagation delays through the logical gates and buffers and delays caused by parasitic impedance of long wires. The final synchronised version of the feedback clock signal CKf is output at the end of every branch of the clock tree. The delay produced by the VCDL 102 is variable and controllable through a variable control voltage Vc applied to the VCDL 102. The ability to vary the delay produced by the VCDL 102 is used by the DLL 100 to synchronize the reference clock signal CKref and the feedback clock signal CKf by aligning the rising edges of the clock signals (CKref, CKf).
The phase detector 104 typically generates variable width pulses on the UP and DOWN output signals dependent on the phase difference between the reference clock signal CKref and the feedback clock signal CKf. The variable width pulses on the UP and DOWN output signals are integrated by a charge pump 105 and a loop filter 106 coupled to the output of the charge pump 105 in order to provide the variable control voltage Vc for the VCDL 102. The control voltage Vc determines the delay to be added to the reference clock signal CKref by the VCDL 102 to align the rising edges of the feedback clock signal CKf and reference clock signal CKref. Together, charge pump 105 and loop filter 106 constitute a control voltage generator 107.
FIG. 2 is a graph illustrating a typical control voltage Vc vs. controlled delay characteristic. The characteristic is non-linear and includes a flat region 202, an optimum region 200 and a steep region 204. In the flat region 202, a wide variation in the control voltage Vc is required for a relatively small delay range.
In the steep region 204, a small variation in the control voltage Vc provides a large delay range. Thus, the VCDL has a very high sensitivity in the steep region 204 because a small noise disturbance on the control voltage Vc results in a large variation in delay resulting in an increase in clock jitter. It is also more difficult to provide stable, non-oscillating loop operation with such a high sensitivity.
In the “optimum region” 200, the change in delay with respect to change in control voltage is moderate. Thus, the DLL 100 operates in the “optimum region” without oscillating, drifting or accumulating noise.
A lock point is any point in the characteristic to which a DLL can lock. There can be a plurality of lock points on the characteristic. The operating point is the lock point to which the DLL is locked during normal operation. One important aspect in designing a DLL is choosing the correct operating point in the characteristic and steering the DLL to reach and lock to that operating point quickly after power-up or reset. This process is typically referred to as DLL initialization. Proper initialization of the DLL ensures good DLL performance and a steady lock.
Selecting the correct operating point sets the control voltage Vc to a target voltage level related to a stable operation region. To ensure stable DLL operation, the DLL should be initialized to an operating point in the “optimum region” 200 of the VCDL delay vs. control voltage characteristic.
After the DLL has reached the operating point, the operating point can move due to changes in operating conditions such as temperature and power supply. Thus, another important aspect of DLL design is to keep the operating point within predetermined limits of the lock point on the delay vs. voltage characteristic while operating conditions change. The variation in the control voltage Vc is limited to the variation in power supply voltage at most, often the variation in the control voltage Vc is smaller than the variation in the power supply voltage. Therefore, the delay vs. control voltage characteristic shown in FIG. 2 is not infinite on both ends and it is possible that as operating conditions change, the operating point can drift to either the left or right limit of the characteristic and the DLL will eventually lose lock. This has a particularly high probability of occurring if the DLL is initialised to an operating point that is too close to either of the two ends of the characteristic.
It is preferable to lock the operating point to a lock point on the left side of the characteristic because this is the region with better noise immunity. However, if the operating point is too close to the left end of the characteristic, it is possible for the DLL to reach the left limit of the characteristic due to changes in operating conditions. This situation is illustrated in FIGS. 3A and 3B.
FIG. 3A is a graph illustrating a lock point 300 that is close to the left end of the control voltage v. delay characteristic. FIG. 3B is a clock signal timing diagram corresponding to the control voltage v. delay characteristic in FIG. 3A. The operating point is at lock point 300 in nominal conditions. A range of delay 302 in the VCDL is required to compensate for variations in operating conditions. Referring to the clock signal timing diagram, the drift in the rising edge of the feedback clock signal CKf 304 corresponds to the range of delay 302 shown in the graph in FIG. 3A. The minimum delay 306 in the delay range 302 is beyond the full range of delays produced by the VCDL 310 as illustrated by the gap in the delay range 308. Thus, the operating point can move to the end of the VCDL range causing the DLL to lose lock.
Another potential risk is for the DLL to start searching for a lock point from a random point on the characteristic during start-up with no restriction on the search direction. As the externally supplied clock signal CK is free running, the initial phase relationship between the feedback clock signal CKf and the reference clock signal CKref after a reset or power-up is not known. Also, after power-up or reset, the position of the initial DLL unlocked operating point is unknown and can be anywhere on the characteristic. Thus, the VCDL delay can be initially increased or decreased dependent on whether the rising edge of the feedback clock signal CKf or the rising edge of the reference clock signal CKref is detected first by the PD 104 (FIG. 1). Therefore, the direction in which the VCDL delay is initially adjusted is unpredictable.
FIG. 4A is a graph illustrating an initial search for a lock point in a search direction that results in hitting the delay limit of the VCDL 102 (FIG. 1) before lock can be reached. FIG. 4B is a clock signal timing diagram corresponding to the search shown in FIG. 4A. The search for the lock point begins at random search point 400. If the DLL starts from a point close to an end of the characteristic and proceeds towards that end, it can hit the delay limit of the VCDL before lock can be reached. In the example shown in FIGS. 4A-4B, during initialization, the DLL unpredictably moves toward the nearest lock point 402 which is beyond the VCDL range and cannot be reached. For example, this situation can occur if the phase detector 104 (FIG. 1) initially produces UP/DOWN pulses that steer the DLL 100 in the direction of the closest lock point 402 that is beyond the VCDL range 310.
The range of the variable VCDL delay in a DLL is also important. Normally, the range of variable VCDL delay is calculated so that the smallest delay corresponds to a clock frequency somewhat higher than that which the DLL specification requires and the largest delay corresponds to a somewhat lower clock frequency. The variable VCDL delay is calculated in order to ensure margins. For a DLL that is designed to operate over a wide clock frequency range, that is, when the clock period is not a constant value and all the possible values are to be accommodated by the same VCDL, the VCDL has to produce an even wider range of delays. As a result, typically there are a number of possible lock points on the VCDL characteristic for a clock signal having a particular frequency. For higher clock frequencies, the VCDL can produce a delay that is longer than a multiple of the clock period. The goal is to lock to the point that can ensure a stable lock condition and low output clock jitter. In most cases, the delay range for the VCDL is chosen so that the number of possible lock points on the DLL characteristic is more than 2 but not more than about 3 to 5. If there are too many lock points they will co-exist together closely on the characteristic and, if disturbed by noise, the DLL can start to jump from one lock point to another, thereby temporarily losing lock.